April 25-27, 2018, Budapest, Hungary

21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

The IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems provides a forum for exchanging ideas, discussing research results, and presenting practical applications in the areas of design, test, and diagnosis of electronic circuits and systems. The DDECS Symposium series has been organized by these European countries: Hungary (2001, 2005), Austria (2010), Germany (2011,2017), Estonia (2012), Czech Republic (1997, 2002, 2006, 2009, 2013), Poland (1998, 2003, 2007, 2014), Serbia (2015) and Slovakia (2000, 2004, 2008, 2016).

Call For Papers


Prospective authors are cordially invited to submit original papers to the Symposium. Papers in English with a length of 6 pages maximum in IEEE conference style are expected. Specialized student and industrial sessions, as well as embedded tutorials, will be organized at the symposium. Accepted papers will be included in the Symposium Proceedings and submitted for inclusion into IEEE Xplore as well as other Abstracting and Indexing databases (WoS, Scopus, etc). An extra work-in-progress session will be targeted to get early feedback on in-progress research and preliminary results (these papers will not be included in IEEE Xplore).

Topics

DDECS covers the areas of design and testing of electronic components, both digital and analog. The topics include the following but are not limited to:

  • SoC and NoC Design and Test
  • ASIC/FPGA Design
  • Built-in Self-Test and Self-Repair
  • Bio-Inspired Hardware
  • Design Verification/Validation
  • Formal Methods in System Design
  • Hardware/Software Co-Design
  • IP-based Design
  • Logic Synthesis
  • Defect/Fault Tolerance and Reliability
  • Design and Test in Nano-Technologies
  • Analog, Mixed-Signal, RF Design and Test
  • ATE Hardware and Software
  • Design for Testability and Diagnosis
  • On-line Testing
  • Embedded Systems
  • Memory, Processor Testing
  • MEMS Testing
  • Physical Design
  • Cyber Physical Systems

Committees



Topic Chairs

Steering Committee

  • V. Stopjaková chair (SK)
  • M. Baláž (SK)
  • T. Garbolino (PL)
  • E. Hrynkiewicz (PL)
  • H. Manhaeve (BE)
  • O. Novák (CZ)
  • A. Pataricza (HU)
  • A. Pawlak (PL)
  • W. Pleskacz (PL)
  • J. Raik (EE)
  • M. Renovell (FR)
  • L. Sekanina (CZ)
  • Z. Stamenković (DE)
  • A. Steininger (AT)
  • H.T. Vierhaus (DE)
  • K. Vlček (CZ)

Program Committee

  • W. Anheier (DE)
  • D. Arbet (SK)
  • M. Balaz (SK)
  • M. Barragan (FR)
  • A. Bosio (FR)
  • G. Cserey (HU)
  • M. Daněk (CZ)
  • M. Dietrich (DE)
  • R. Drechsler (DE)
  • M. Drutarovsky (SK)
  • P. Ellervee (EE)
  • G. Fey (DE)
  • P. Fišer (CZ)
  • M. Fuegger (FR)
  • T. Garbolino (PL)
  • P. Girard (FR)
  • D. Gizopoulos (GR)
  • S. Hellebrand (DE)
  • E. Hrynkiewicz (PL)
  • K. Jelemenska (SK)
  • G. Jervan (EE)
  • D. Kasprowicz (PL)
  • P. Kitsos (GR)
  • R. Kraemer (DE)
  • A. Krasniewski (PL)
  • M. Krstic (DE)
  • H. Kubatova (CZ)
  • W. Kuzmicz (PL)
  • E. Larsson (SE)
  • R. Leveugle (FR)
  • D. Macko (SK)
  • H. Manhaeve (BE)
  • C. Metra (IT)
  • L. Miclea (RO)
  • L. Nagy (SK)
  • O. Novak (CZ)
  • S. Ohtake (JP)
  • A. Pataricza (HU)
  • A. Pawlak (PL)
  • Z. Peng (SE)
  • L. Pierre (FR)
  • S. Piestrak (FR)
  • W. Pleskacz (PL)
  • A. Pleštil (CZ)
  • T. Polzer (AT)
  • P. Prinetto (IT)
  • Z. Raida (CZ)
  • J. Raik (EE)
  • B. Rouzeyre (FR)
  • R. Růžička (CZ)
  • S. Sattler (DE)
  • P. Schneider (DE)
  • M. Schölzel (DE)
  • L. Sekanina (CZ)
  • M. Sonza Reorda (IT)
  • J. Sosnowski (PL)
  • Z. Stamenković (DE)
  • A. Steininger (AT)
  • G. Stojanovic (RS)
  • V. Stopjakova (SK)
  • O. Šubrt (CZ)
  • K. Tammemäe (EE)
  • M. Taouil (NL)
  • P. Teixeira (PT)
  • R. Ubar (EE)
  • M. Udrescu (RO)
  • D. Vázquez (ES)
  • H.T. Vierhaus (DE)
  • K. Vlcek (CZ)
  • R. Wille (AT)
  • H.J. Wunderlich (DE)
  • M. Zachariasova (CZ)
  • Y. Zorian (US)

Submission


Camera-Ready Version (due April 1, 2018)

The camera-ready papers are uploaded using ConfTool.

The camera-ready papers also have to be uploaded using IEEE CPS.

All the accepted papers (oral presentations as well as poster presentations) will be included in the proceedings and will be published in the IEEE Xplore digital library, except for the work-in-progress papers.

The final manuscript length of the accepted papers is 6 pages in case of regular papers (both oral and poster presentations) and 4 pages in case of student papers.

In order to prepare the camera-ready version of your paper please follow these steps:

Authors' not following the instructions may result in their paper not being included in the proceedings.

Work-in-progress Papers

The Work-in-progress papers are uploaded using ConfTool.

The Work-in-progress papers will be accepted for oral presentation. At least one author of the paper is required to register and pay the work-in-progress registration fee and to present the paper. These papers will be included in the Informal DDECS 2018 Proceedings with a non-IEEE ISBN number. The Proceedings will be distributed electronically to all DDECS 2018 participants.

Poster and Oral Presentation Preparation

The Posters are uploaded using ConfTool.

The Posters also have to be uploaded using IEEE CPS.

Poster Size A0 - portrait format (height 1189 mm, width 841 mm). Material for fixing the poster will be provided.

Paper Format

Papers can be submitted in the following categories:

The authors are requested to select one of the above categories during the submission process in ConfTool.

The submitted papers must meet the following conditions:

The format of the paper should follow the IEEE guidelines for the two-column IEEE-sponsored conference proceedings. Templates for Microsoft Word and LaTeX are available here.

Paper Acceptance (due March 15, 2018)

Papers will be accepted for either oral presentation or poster presentation. At least one of the authors of accepted papers will agree to register for and participate in DDECS 2018 for oral presentation or poster presentation.

Program


Wednesday 25/Apr/2018
8:00am - 9:00am Registration
9:00am - 9:15am Opening Session
9:15am - 10:15am

Keynote 1: Ultra-Fast Wireless Communication with 100Gb/s and Beyond

Chair: Zoran Stamenkovic, IHP

10:30am - 11:30am

Poster Session 1: Posters & Coffee Break

  • Theodor Hillebrand, Ludwig Karsthof, Steffen Paul, Dagmar Peters-Drolshagen:
    Reliability-aware Multi-Vth Domain Digital Design Assessment

  • Lukas Kohutka, Viera Stopjakova: Heap Queue:
    A Novel Efficient Hardware Architecture of MIN/MAX Queues for Real-Time Systems

  • Yuanqing Li, Anselm Breitenreiter, Marko Andjelkovic, Oliver Schrape, Milos Krstic:
    Flip-Flop SEUs Mitigation Through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle

  • Ondrej Novak:
    Nonlinear Binary Codes and Their Utilization for Test

  • Siavoosh Payandeh Azad, Adeboye Stephen Oyeniran, Raimund Ubar:
    Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells

  • Dominik Macko:
    Contribution to Automated Generating of System Power-Management Specification

  • Izel Cagin Odabasi, Mustafa Berke Yelten, Engin Afacan, Faik Baskaya, Ali Emre Pusane, Gunhan Dundar:
    A Rare Event Based Yield Estimation Methodology for Analog Circuits
11:30am - 1:00pm

Session 1: Analog Design

Chair: Witold Pleskacz, Warsaw University of Technology

  • Said Hamid Fani, Ali Peiravi, Farshad Moradi, Hooman Farkhani:
    A Novel TFET 8T-SRAM Cell With Improved Noise Margin and Stability

  • Daniel Arbet, Martin Kováč, Lukáš Nagy, Viera Stopjaková, Michal Šovčík:
    Two-Stage Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications

  • Lukas Nagy, Daniel Arbet, Martin Kovac, Miroslav Potocny, Viera Stopjakova:
    Design and Performance Analysis of Ultra-Low Voltage Rail-to-Rail Comparator in 130 nm CMOS Technology
1:00pm - 2:00pm Lunch
2:00pm - 3:30pm

Session 2: System Design

Chair: Manfred Dietrich, Dikuli Unternehmensberatung

  • Amila Akagic, Emir Buza, Razija Turcinhodzic, Hana Haseljic, Hiroyuki Noda, Hideharu Amano:
    Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC

  • Kai Lehniger, Stefan Weidling, Mario Schoelzel:
    Heuristic for Page-based Incremental Reprogramming of Wireless Sensor Nodes

  • Serhiy Avramenko, Siavoosh Payandeh Azad, Stefano Esposito, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin:
    QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications
3:30pm - 4:00pm Coffee Break
4:00pm - 5:30pm

Session 3: Digital Circuit Test

Chair: Ondrej Novak, TU Liberec

  • Alexander Sprenger, Sybille Hellebrand:
    Tuning Stochastic Space Compaction to Faster-than-At-Speed Test

  • Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen:
    Constraint-based Pattern Retargeting for Reducing Localized Power Activity during Testing

  • Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
    On the Comparison of Different ATPG approaches for Approximate Integrated Circuits
7:00pm - 9:00pm Welcome Dinner
Thursday 26/Apr/2018
8:00am - 9:00am Registration
9:00am - 10:00am

Keynote 2: Complete Defect Oriented Test & Diagnosis of Logic Designs

Chair: Viera Stopjakova, Slovak University of Technology

10:00am - 11:00am

Poster Session 2: Posters & Coffee Break

  • Giulio D'Amato, Gianfranco Avitabile, Claudio Talarico, Giovanni Piccinni, Giuseppe Coviello:
    An integrated phase shifting frequency synthesizer for active electronically scanned arrays

  • Sara Divanbeigi, Felix Winkler, Martin Bergen, Markus Olbrich:
    Modeling And Accelerated Mixed-Signal Simulation Of A Control System

  • David Lemma, Daniel Große, Rolf Drechsler:
    Natural Language based Power Domain Partitioning

  • Umberto Ferrandino, Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Petr Fišer, Alberto Bosio:
    Synthesis of Finite State Machines on Memristor Crossbars

  • Szymon Reszewicz, Krzysztof Siwiec, Witold Pleskacz:
    2.4 GHz LC-VCO with improved robustness against PVT using FD-SOI body biasing techniqe

  • Abraham Temesgen Tibebu, Goerschwin Fey:
    Augmenting All Solution SAT Solving for Circuits with Structural Information

  • Milan Dinčić, Zoran Perić, Dragan Denić, Zoran Stamenković:
    Design of low-bit robust analog-to-digital converters for signals with Gaussian distribution
11:00am - 12:00pm

Session 4: Reconfigurability

Chair: Alberto Bosio, LIRMM

  • Riccardo Cantoro, Luigi San Paolo, Matteo Sonza Reorda, Giovanni Squillero:
    New Techniques for Reducing Duration of Reconfigurable Scan Network Test

  • Hassan Ebrahimi, Hans G. Kerkhoff:
    Intermittent Resistance Fault Detection at Board Level
12:00pm - 1:00pm

Session 5: Reliability

Chair: Liviu-Cristian Miclea, Technical University of Cluj-Napoca

  • Florian Huemer, Thomas Polzer, Andreas Steininger:
    Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA

  • Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Goerschwin Fey:
    Software-Level TMR Approach for On-Board Data Processing in Space Applications
1:00pm - 2:00pm Lunch
3:30pm - 10:00pm Social event
Friday 27/Apr/2018
8:00am - 9:00am Registration
9:00am - 10:00am

Keynote 3: Design of Computing Architectures for Emerging Nanoelectronic Devices

Chair: Andreas Steininger, Vienna University of Technology

10:00am - 11:00am

Session 6: Student Papers

Chair: Mario Schölzel, IHP

  • Omar Farag, Mariam Mohamed Fouad, Mohamed Abdelghany:
    Integerated sensors for early breast cancer diagnostics

  • Miroslav Potocny, Viera Stopjaková, Martin Kováč:
    Self Vth-compensating CMOS on-chip rectifier for inductively powered implantable medical devices

  • Navaneetha Channiganathota Manjappa, Anselm Breitenreiter, Markus Ulbricht, Miloš Krstić:
    A Methodology to Verify Digital IP's Within Mixed-Signal Systems
11:00am - 11:30am Coffee Break
11:30am - 12:30pm

Session 7: Work in Progress

Chair: Gyorgy Cserey, Pazmany Peter Catholic University

  • Ondrej Cekan, Zdenek Kotasek:
    Random Test Generation Through a Probabilistic Constrained Grammar

  • Jakub Podivinsky, Jakub Lojda, Zdenek Kotasek:
    FPGA-based Robot Controller: An Experimental Evaluation of Fault Tolerance Properties

  • Michal Šovčík, Viera Stopjaková:
    Digital Calibration of Operational Amplifiers for Low-Voltage and Low-Power Applications

  • Daniel Hajto, Adam Rak, Sandor Foldi, Gyorgy Cserey:
    SPICE model for CMOS based memristor implementation

  • David Matousek, Jiri Hospodka, Ondrej Subrt:
    New Variant of a Negative 4-phase Chage Pump
12:30pm - 1:00pm Closing Session
1:00pm - 2:00pm Lunch

Keynote Speakers


Registration


General Rules

Early registration for DDECS 2018 will be available until April 1st, 2018. Early registrations are subject to substantial discount. Authors are required to register and make the payment not later than the early registration deadline. Otherwise the Author's submission will not be published in the proceedings. In order to be published in the conference proceedings, each accepted regular paper must be accompanied by at least one regular registration. Each accepted student paper must be accompanied by at least one student or regular registration. Student registration is only available to presenters of student papers.

Registration type Early registration (by April 1, 2018) Late registration (after April 1, 2018)
Regular non-IEEE member 560€ 670€
Regular IEEE member 430€ 580€
Student non-IEEE member 340€ 460€
Student IEEE member 310€ 410€
IEEE life member 310€ 410€

All registration fees include:

Additional fees

The registration is available now! Please register with ConfTool.

Venue


Hotel NH Budapest City

The NH Budapest City hotel is in the Újlipótváros business district on the Pest side of the river. Some of Budapest’s star attractions are right on the doorstep, and the nearby metro station whisks you to more tourist hotspots.

  • a 10-minute walk to the Danube River and famous Parliament building
  • close to Margaret Island, for tranquil walks and cycle rides
  • a metro ride away from the castle and synagogue

The hotel’s 160 rooms are all of a Standard type – they’re simply furnished but very comfortable. They have satellite TVs and tea and coffee-making facilities.

  • top-quality mattresses
  • free Wi-Fi
  • 2 wheelchair-accessible rooms

For conferences and business meetings, the hotel has a handful of function rooms. The restaurant serves top-quality à la carte meals, while the friendly bar is the place to go to sample Hungarian wine. The hotel has also a handy gym and sauna.

  • food available 24 hours a day
  • gym, sauna and relaxation chairs
  • private parking

Accommodation


NH Hotel

Other Hotel suggestions

Travel


By Train

Arrival at the Keleti train station

You can take the metro line 2 from the Keleti railway station to get to the station "Blaha Lujza tér". From there take the tram line 4/6 for the station "Jászai Mari tér". You can reach the hotel in a walking distance from about 4 minutes.

Arrival at the Nyugati train station

Exit the station and turn right for the street "Szent Istvan Krt". From there please turn right again for the street "Hegedüs Gyula". Afterwards please turn left for the street "Vigszinhaz". The hotel is located on the right.

By Airplane

Arrival at the Liszt Ferenc Budapest airport
  • Taxi: It´s a 40 minutes trip.
  • Public transportation: You can take the bus line 200 from the Airport Budapest, station "Repüloter, P+R" to get to the station "Kobanya-Kispest". From there take the metro line M3 (blue line) for the station "Nyugati Palyaudvar". You can reach the hotel in a walking distance from about 5 minutes. It's a 60 minutes trip.

By Car

The hotel's GPS Coordinates: 47.512896°N 19.051955°E

Parking: Offsite is €1,40+VAT / hour or onsite is €1,80+VAT / hour or €20+VAT / day.

ddecs@itk.ppke.hu

H-1083 Budapest, Práter utca 50/a.